In a RHBD 11T memory cell, this still stores value by blocking the feedback path to prevent the induced transient impulse that affects the next nodes. Nevertheless, for this RHBD 11T memory cell, due to the single-ended structure, differential writing and reading capabilities are not enabled, which may increase the operating time. In a DICE memory cell, it is proposed using 12 transistors, which uses two interlocked latch pair to store the complementary values so that the effected values can be recovered to its original value using positive feedbacks. Redesigning a cell structure and using a shallow trench insulation technique, a RHBD 12T memory cell is proposed at the cost of large area above the head. However, the common disadvantage of 11T, Dice and 12T cells indicate that their general areas are larger.
Hence, all the previous RHBD cells are not suitable for aerospace applications in which the RHBD memory cells with efficient area and high reliability properties are necessary to offer appropriate designs reliability systemsIn order to solve this contradiction, a novel area-efficient, lowpower,and high-reliability RHBD 10T memory cell is proposedusing a circuit-level hardening technique. According to SEU physicaltheory together with reasonable transistor size, it can provide highradiation hardening capability at the cost of write and read accesstimes.Intuitively, this brief is mainly organized as follows. Section IIdescribes the schematic of the proposed RHBD 10T memory cell,and provides the analysis of its timing and fault-tolerate recovery.
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